1. Field of the Invention
This invention relates to improvements in semiconductor fabrication techniques and devices made thereby, and, more particularly, to improvements in methods for making depletion NMOS capacitors in logic processes in which embedded DRAM logic devices are formed.
2. Relevant Background
With increasing integration of multiple integrated circuit functions onto a single semiconductor chip, the need for smaller memory cells to embed in logic processes has arisen. A 1T-LC DRAM cell is presently regarded as the cell of choice for embedding, due to its small size. Typically the DRAM cell is implemented in a single polysilicon, double metal Logic CMOS process using a planar MOS capacitor. The capacitor may be an NMOS or a PMOS capacitor in the enhancement or depletion mode. In fact, enhancement mode capacitors already exist in many known CMOS processes.
In an NMOS cell with an enhancement capacitor, the field-plate is connected to V.sub.DD and P.sub.sub is connected to ground to create an inversion layer to store the charge. The amount of charge that may be stored in such an enhancement capacitor is reduced, since the inversion layer disappears for storage node voltage above V.sub.DD -V.sub.T (V.sub.T is the threshold voltage of the capacitor). This situation arises for a dual-gate oxide cell, in which the pass gate can be at a higher bias (V.sub.PP) than the capacitor plate (V.sub.DD). Thus, maximum possible charge storage is achieved by a depletion capacitor which maintains an inversion layer, even at storage node is V.sub.DD. Since charge stored per unit area of capacitor is increased significantly, allowing reduction in capacitor area and cell size. Another concern with an NMOS enhancement mode storage capacitor is that the voltage slew that may occur on power supplies changes the amount of charge stored in the cell, which may result in an erroneous read. By using a depletion mode capacitor, the field plate may be connected to ground for an NMOS capacitor. Since the field plate and the capacitor substrate are then connected to the same power supply, there is no change in charge stored, even with voltage slew. However, implementing a depletion mode capacitor may require an additional pattern and implant step, so that only the depletion capacitor receives the depletion implant. This adds to cost and complexity of the process.